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%.1o,%.2o,%.3o,%.4o,%.5o%34a %lcannot create backend for elf filecannot get section header string table index%s%%7m %s%%.1o,%s%%.2o,%s%%.3o,,%s%%.4o%s%%.5o%%34a %s%%l%s%s%s: file format not recognized%s: File format not recognizedDisplay relocation information.Display the full contents of all sections requestedDisplay assembler code of executable sectionsOnly display information for section NAME.https://sourceware.org/bugzilla[FILE...]Show information from FILEs (a.out by default).eblopenbackend.cresult->destr != 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" PQcs________````````h`8a8a8a8a8a8a8a8a8a8aaaaaaa________p_p_p_p_p_p_p_p_a`a`a`a`a`a`aaa``aa```0`0`axdxcxbxsidibpsp A@  !P@@ @ @ @(@0 @8 @@ @H@P@X@`@h@@31@@4:@526ia64_reloc_valid_use '4DTdt .APar 0E\s&9IYiy.<KZj|#6I\R_IA64_NONER_IA64_IMM14R_IA64_IMM22R_IA64_IMM64R_IA64_DIR32MSBR_IA64_DIR32LSBR_IA64_DIR64MSBR_IA64_DIR64LSBR_IA64_GPREL22R_IA64_GPREL64IR_IA64_GPREL32MSBR_IA64_GPREL32LSBR_IA64_GPREL64MSBR_IA64_GPREL64LSBR_IA64_LTOFF22R_IA64_LTOFF64IR_IA64_PLTOFF22R_IA64_PLTOFF64IR_IA64_PLTOFF64MSBR_IA64_PLTOFF64LSBR_IA64_FPTR64IR_IA64_FPTR32MSBR_IA64_FPTR32LSBR_IA64_FPTR64MSBR_IA64_FPTR64LSBR_IA64_PCREL60BR_IA64_PCREL21BR_IA64_PCREL21MR_IA64_PCREL21FR_IA64_PCREL32MSBR_IA64_PCREL32LSBR_IA64_PCREL64MSBR_IA64_PCREL64LSBR_IA64_LTOFF_FPTR22R_IA64_LTOFF_FPTR64IR_IA64_LTOFF_FPTR32MSBR_IA64_LTOFF_FPTR32LSBR_IA64_LTOFF_FPTR64MSBR_IA64_LTOFF_FPTR64LSBR_IA64_SEGREL32MSBR_IA64_SEGREL32LSBR_IA64_SEGREL64MSBR_IA64_SEGREL64LSBR_IA64_SECREL32MSBR_IA64_SECREL32LSBR_IA64_SECREL64MSBR_IA64_SECREL64LSBR_IA64_REL32MSBR_IA64_REL32LSBR_IA64_REL64MSBR_IA64_REL64LSBR_IA64_LTV32MSBR_IA64_LTV32LSBR_IA64_LTV64MSBR_IA64_LTV64LSBR_IA64_PCREL21BIR_IA64_PCREL22R_IA64_PCREL64IR_IA64_IPLTMSBR_IA64_IPLTLSBR_IA64_COPYR_IA64_SUBR_IA64_LTOFF22XR_IA64_LDXMOVR_IA64_TPREL14R_IA64_TPREL22R_IA64_TPREL64IR_IA64_TPREL64MSBR_IA64_TPREL64LSBR_IA64_LTOFF_TPREL22R_IA64_DTPMOD64MSBR_IA64_DTPMOD64LSBR_IA64_LTOFF_DTPMOD22R_IA64_DTPREL14R_IA64_DTPREL22R_IA64_DTPREL64IR_IA64_DTPREL32MSBR_IA64_DTPREL32LSBR_IA64_DTPREL64MSBR_IA64_DTPREL64LSBR_IA64_LTOFF_DTPREL22IA_64_ARCHEXTIA_64_UNWINDIA_64_HP_OPT_ANOTIA_64_HP_HSL_ANOTIA_64_HP_STACKIA_64_PLT_RESERVEIA_64_EXT [ZZZ$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[$[ [ZZZar.FPUbranchspecialNATpredicaterscbspbspstorernatfcreflagcsdssdcflgfsrfirfdrccvunatfpsritcpfslcecvfpvrapprippsrcfm__^__________________________________@_pdccpd6cpdpdpdpdpdpdpdpdpdpd6c6cpdpdcpdpdpdcpdpdpdpdpdpdpd6cpdcpdpd6cpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpdpd6cx XYZ[alpha_reloc_valid_use.>N]l{(:HXi{R_ALPHA_NONER_ALPHA_REFLONGR_ALPHA_REFQUADR_ALPHA_GPREL32R_ALPHA_LITERALR_ALPHA_LITUSER_ALPHA_GPDISPR_ALPHA_BRADDRR_ALPHA_HINTR_ALPHA_SREL16R_ALPHA_SREL32R_ALPHA_SREL64R_ALPHA_GPRELHIGHR_ALPHA_GPRELLOWR_ALPHA_GPREL16R_ALPHA_COPYR_ALPHA_GLOB_DATR_ALPHA_JMP_SLOTR_ALPHA_RELATIVER_ALPHA_TLS_GD_HIR_ALPHA_TLSGDR_ALPHA_TLS_LDMR_ALPHA_DTPMOD64R_ALPHA_GOTDTPRELR_ALPHA_DTPREL64R_ALPHA_DTPRELHIR_ALPHA_DTPRELLOR_ALPHA_DTPREL16R_ALPHA_GOTTPRELR_ALPHA_TPREL64R_ALPHA_TPRELHIR_ALPHA_TPRELLOR_ALPHA_TPREL16ALPHA_PLTRO_GLOBAL_OFFSET_TABLE_X_]]X_6^X_X_X_X_X_X_X_X_X_X_6^6^X_]]X_X_X_]X_X_X_X_X_X_X_6^X_^X_X_6^X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_6^p !P`^^^^^^^^^^^^^^^^^^^^^^^^__ _@_P_h_______________________`````````` `0`P`p`@^ @ @@@B@bbwxfixcix0x080x100x200x400x80maxprecise_traparm_reloc_valid_use #/:FRalz%4DS`lx&<JXcq~'7O^n~'7GWjz 0@Scs%6ETfz!9QfvR_ARM_NONER_ARM_PC24R_ARM_ABS32R_ARM_REL32R_ARM_PC13R_ARM_ABS16R_ARM_ABS12R_ARM_THM_ABS5R_ARM_ABS8R_ARM_SBREL32R_ARM_THM_PC22R_ARM_THM_PC8R_ARM_AMP_VCALL9R_ARM_TLS_DESCR_ARM_THM_SWI8R_ARM_XPC25R_ARM_THM_XPC22R_ARM_TLS_DTPMOD32R_ARM_TLS_DTPOFF32R_ARM_TLS_TPOFF32R_ARM_COPYR_ARM_GLOB_DATR_ARM_JUMP_SLOTR_ARM_RELATIVER_ARM_GOTOFFR_ARM_GOTPCR_ARM_GOT32R_ARM_PLT32R_ARM_CALLR_ARM_JUMP24R_ARM_THM_JUMP24R_ARM_BASE_ABSR_ARM_ALU_PCREL_7_0R_ARM_ALU_PCREL_15_8R_ARM_ALU_PCREL_23_15R_ARM_LDR_SBREL_11_0R_ARM_ALU_SBREL_19_12R_ARM_ALU_SBREL_27_20R_ARM_TARGET1R_ARM_SBREL31R_ARM_V4BXR_ARM_TARGET2R_ARM_PREL31R_ARM_MOVW_ABS_NCR_ARM_MOVT_ABSR_ARM_MOVW_PREL_NCR_ARM_MOVT_PRELR_ARM_THM_MOVW_ABS_NCR_ARM_THM_MOVT_ABSR_ARM_THM_MOVW_PREL_NCR_ARM_THM_MOVT_PRELR_ARM_THM_JUMP19R_ARM_THM_JUMP6R_ARM_THM_ALU_PREL_11_0R_ARM_THM_PC12R_ARM_ABS32_NOIR_ARM_REL32_NOIR_ARM_ALU_PC_G0_NCR_ARM_ALU_PC_G0R_ARM_ALU_PC_G1_NCR_ARM_ALU_PC_G1R_ARM_ALU_PC_G2R_ARM_LDR_PC_G1R_ARM_LDR_PC_G2R_ARM_LDRS_PC_G0R_ARM_LDRS_PC_G1R_ARM_LDRS_PC_G2R_ARM_LDC_PC_G0R_ARM_LDC_PC_G1R_ARM_LDC_PC_G2R_ARM_ALU_SB_G0_NCR_ARM_ALU_SB_G0R_ARM_ALU_SB_G1_NCR_ARM_ALU_SB_G1R_ARM_ALU_SB_G2R_ARM_LDR_SB_G0R_ARM_LDR_SB_G1R_ARM_LDR_SB_G2R_ARM_LDRS_SB_G0R_ARM_LDRS_SB_G1R_ARM_LDRS_SB_G2R_ARM_LDC_SB_G0R_ARM_LDC_SB_G1R_ARM_LDC_SB_G2R_ARM_MOVW_BREL_NCR_ARM_MOVT_BRELR_ARM_MOVW_BRELR_ARM_THM_MOVW_BREL_NCR_ARM_THM_MOVT_BRELR_ARM_THM_MOVW_BRELR_ARM_TLS_GOTDESCR_ARM_TLS_CALLR_ARM_TLS_DESCSEQR_ARM_THM_TLS_CALLR_ARM_PLT32_ABSR_ARM_GOT_ABSR_ARM_GOT_PRELR_ARM_GOT_BREL12R_ARM_GOTOFF12R_ARM_GOTRELAXR_ARM_GNU_VTENTRYR_ARM_GNU_VTINHERITR_ARM_THM_PC11R_ARM_THM_PC9R_ARM_TLS_GD32R_ARM_TLS_LDM32R_ARM_TLS_LDO32R_ARM_TLS_IE32R_ARM_TLS_LE32R_ARM_TLS_LDO12R_ARM_TLS_LE12R_ARM_TLS_IE12GPR_ARM_ME_TOOR_ARM_THM_TLS_DESCSEQ16R_ARM_THM_TLS_DESCSEQ32R_ARM_THM_GOT_BREL12R_ARM_IRELATIVER_ARM_RXPC25R_ARM_RSBREL32R_ARM_THM_RPC22R_ARM_RREL32R_ARM_RABS22R_ARM_RPC24R_ARM_RBASEARM_EXIDXARM_PREEMPTMAPARM_ATTRIBUTESARM_TFUNC$d. FPAVFPslpprcorig_r0fpscr @ `` @ bswphalfthumb26bitfast-multfpavfpedspjavaiwmmxtaeabiCPU_raw_nameCPU_nameCPU_archCPU_arch_profileApplicationRealtimeMicrocontrollerARM_ISA_useTHUMB_ISA_useWMMX_archAdvanced_SIMD_archPCS_configABI_PCS_R9_useABI_PCS_RW_dataABI_PCS_RO_dataABI_PCS_GOT_useABI_PCS_wchar_tABI_FP_roundingABI_FP_denormalABI_FP_exceptionsABI_FP_user_exceptionsABI_FP_number_modelABI_align8_neededABI_align8_preservedABI_enum_sizeABI_HardFP_useABI_VFP_argsABI_WMMX_argsABI_optimization_goalsABI_FP_optimization_goalsCPU_unaligned_accessVFP_HP_extensionABI_FP_16bit_formatnodefaultsalso_compatible_withT2EE_useconformanceVirtualization_useMPextension_useNoneIEEE 754Alternative FormatNot Allowedv6Prefer SpeedAggressive SpeedPrefer SizeAggressive SizePrefer AccuracyAggressive AccuracyPrefer DebugAggressive DebugAAPCSWMMX registerscustomVFP registersas VFP_archSP onlyDP onlySP and DPUnusedsmallforced to intNoYes, except leaf SPYes4-byteFiniteRTABINeededSign onlyGOT-indirectAbsolutePC-relativeSB-relativeV6SBTLSBare platformLinux applicationLinux DSOPalmOS 2004PalmOS (reserved)SymbianOS 2004SymbianOS (reserved)NEONv1WMMXv1WMMXv2VFPv1VFPv2VFPv3VFPv3-D16Thumb-1Thumb-2Pre-v4v4Tv5Tv5TEv5TEJv6KZv6T2v6Kv7v6-Mv6S-MSS S@SSSS TPTTTTU@UpUUUUV@VpVVVW0W`WWWRRWR XRPXRRRRRRRRRRRRRRRRRRRRRRRRRXXXXXRR(ZXX(Z^Y(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z^Y^Y(Z(ZX(Z(Z(ZX(Z(Z(Z(Z(Z(Z(Z^Y(ZY(Z(Z^Y(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z(Z^YpPQRS     dynamic symbols use segment indexmapping symbols precede otherssorted symbol tablessoft-float ABIhard-float ABIBE8LE8interworking enableduses APCS/26uses APCS/floatposition independent8 bit structure alignmentuses new ABIuses old ABIsoftware FPMaverick FPVersion1 EABIVersion2 EABIVersion3 EABIVersion4 EABIVersion5 EABIaarch64_reloc_valid_use #=Tn*Ec} 3DUl4Mi'B^y5Mh#Cc9_ 8 \  A `   - O t  = Z v !0CWjR_AARCH64_ABS64R_AARCH64_ABS32R_AARCH64_COPYR_AARCH64_GLOB_DATR_AARCH64_JUMP_SLOTR_AARCH64_RELATIVER_AARCH64_TLS_DTPMODR_AARCH64_TLS_DTPRELR_AARCH64_TLS_TPRELR_AARCH64_TLSDESCR_AARCH64_NONER_AARCH64_ABS16R_AARCH64_PREL64R_AARCH64_PREL32R_AARCH64_PREL16R_AARCH64_MOVW_UABS_G0R_AARCH64_MOVW_UABS_G0_NCR_AARCH64_MOVW_UABS_G1R_AARCH64_MOVW_UABS_G1_NCR_AARCH64_MOVW_UABS_G2R_AARCH64_MOVW_UABS_G2_NCR_AARCH64_MOVW_UABS_G3R_AARCH64_MOVW_SABS_G0R_AARCH64_MOVW_SABS_G1R_AARCH64_MOVW_SABS_G2R_AARCH64_LD_PREL_LO19R_AARCH64_ADR_PREL_LO21R_AARCH64_ADR_PREL_PG_HI21R_AARCH64_ADR_PREL_PG_HI21_NCR_AARCH64_ADD_ABS_LO12_NCR_AARCH64_LDST8_ABS_LO12_NCR_AARCH64_LDST16_ABS_LO12_NCR_AARCH64_LDST32_ABS_LO12_NCR_AARCH64_LDST64_ABS_LO12_NCR_AARCH64_LDST128_ABS_LO12_NCR_AARCH64_TSTBR14R_AARCH64_CONDBR19R_AARCH64_JUMP26R_AARCH64_CALL26R_AARCH64_MOVW_PREL_G0R_AARCH64_MOVW_PREL_G0_NCR_AARCH64_MOVW_PREL_G1R_AARCH64_MOVW_PREL_G1_NCR_AARCH64_MOVW_PREL_G2R_AARCH64_MOVW_PREL_G2_NCR_AARCH64_MOVW_PREL_G3R_AARCH64_MOVW_GOTOFF_G0R_AARCH64_MOVW_GOTOFF_G0_NCR_AARCH64_MOVW_GOTOFF_G1R_AARCH64_MOVW_GOTOFF_G1_NCR_AARCH64_MOVW_GOTOFF_G2R_AARCH64_MOVW_GOTOFF_G2_NCR_AARCH64_MOVW_GOTOFF_G3R_AARCH64_GOTREL64R_AARCH64_GOTREL32R_AARCH64_GOT_LD_PREL19R_AARCH64_LD64_GOTOFF_LO15R_AARCH64_ADR_GOT_PAGER_AARCH64_LD64_GOT_LO12_NCR_AARCH64_LD64_GOTPAGE_LO15R_AARCH64_TLSGD_ADR_PREL21R_AARCH64_TLSGD_ADR_PAGE21R_AARCH64_TLSGD_ADD_LO12_NCR_AARCH64_TLSGD_MOVW_G1R_AARCH64_TLSGD_MOVW_G0_NCR_AARCH64_TLSLD_ADR_PREL21R_AARCH64_TLSLD_ADR_PAGE21R_AARCH64_TLSLD_ADD_LO12_NCR_AARCH64_TLSLD_MOVW_G1R_AARCH64_TLSLD_MOVW_G0_NCR_AARCH64_TLSLD_LD_PREL19R_AARCH64_TLSLD_MOVW_DTPREL_G2R_AARCH64_TLSLD_MOVW_DTPREL_G1R_AARCH64_TLSLD_MOVW_DTPREL_G1_NCR_AARCH64_TLSLD_MOVW_DTPREL_G0R_AARCH64_TLSLD_MOVW_DTPREL_G0_NCR_AARCH64_TLSLD_ADD_DTPREL_HI12R_AARCH64_TLSLD_ADD_DTPREL_LO12R_AARCH64_TLSLD_ADD_DTPREL_LO12_NCR_AARCH64_TLSLD_LDST8_DTPREL_LO12R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NCR_AARCH64_TLSLD_LDST16_DTPREL_LO12R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NCR_AARCH64_TLSLD_LDST32_DTPREL_LO12R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NCR_AARCH64_TLSLD_LDST64_DTPREL_LO12R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NCR_AARCH64_TLSLD_LDST128_DTPREL_LO12R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NCR_AARCH64_TLSIE_MOVW_GOTTPREL_G1R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NCR_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NCR_AARCH64_TLSIE_LD_GOTTPREL_PREL19R_AARCH64_TLSLE_MOVW_TPREL_G2R_AARCH64_TLSLE_MOVW_TPREL_G1R_AARCH64_TLSLE_MOVW_TPREL_G1_NCR_AARCH64_TLSLE_MOVW_TPREL_G0R_AARCH64_TLSLE_MOVW_TPREL_G0_NCR_AARCH64_TLSLE_ADD_TPREL_HI12R_AARCH64_TLSLE_ADD_TPREL_LO12R_AARCH64_TLSLE_ADD_TPREL_LO12_NCR_AARCH64_TLSLE_LDST8_TPREL_LO12R_AARCH64_TLSLE_LDST8_TPREL_LO12_NCR_AARCH64_TLSLE_LDST16_TPREL_LO12R_AARCH64_TLSLE_LDST16_TPREL_LO12_NCR_AARCH64_TLSLE_LDST32_TPREL_LO12R_AARCH64_TLSLE_LDST32_TPREL_LO12_NCR_AARCH64_TLSLE_LDST64_TPREL_LO12R_AARCH64_TLSLE_LDST64_TPREL_LO12_NCR_AARCH64_TLSLE_LDST128_TPREL_LO12R_AARCH64_TLSLE_LDST128_TPREL_LO12_NCR_AARCH64_TLSDESC_LD_PREL19R_AARCH64_TLSDESC_ADR_PREL21R_AARCH64_TLSDESC_ADR_PAGE21R_AARCH64_TLSDESC_LD64_LO12R_AARCH64_TLSDESC_ADD_LO12R_AARCH64_TLSDESC_OFF_G1R_AARCH64_TLSDESC_OFF_G0_NCR_AARCH64_TLSDESC_LDRR_AARCH64_TLSDESC_ADDR_AARCH64_TLSDESC_CALLx%delrFP/SIMDv%d.got.got.pltAARCH64_BTI_PLTAARCH64_PAC_PLTAARCH64_VARIANT_PCS pstatedbg_infoDBGWVR0_EL1DBGWCR0_EL1DBGWVR1_EL1DBGWCR1_EL1DBGWVR2_EL1DBGWCR2_EL1DBGWVR3_EL1DBGWCR3_EL1DBGWVR4_EL1DBGWCR4_EL1DBGWVR5_EL1DBGWCR5_EL1DBGWVR6_EL1DBGWCR6_EL1DBGWVR7_EL1DBGWCR7_EL1DBGWVR8_EL1DBGWCR8_EL1DBGWVR9_EL1DBGWCR9_EL1DBGWVR10_EL1DBGWCR10_EL1DBGWVR11_EL1DBGWCR11_EL1DBGWVR12_EL1DBGWCR12_EL1DBGWVR13_EL1DBGWCR13_EL1DBGWVR14_EL1DBGWCR14_EL1DBGWVR15_EL1DBGWCR15_EL1DBGBVR0_EL1DBGBCR0_EL1DBGBVR1_EL1DBGBCR1_EL1DBGBVR2_EL1DBGBCR2_EL1DBGBVR3_EL1DBGBCR3_EL1DBGBVR4_EL1DBGBCR4_EL1DBGBVR5_EL1DBGBCR5_EL1DBGBVR6_EL1DBGBCR6_EL1DBGBVR7_EL1DBGBCR7_EL1DBGBVR8_EL1DBGBCR8_EL1DBGBVR9_EL1DBGBCR9_EL1DBGBVR10_EL1DBGBCR10_EL1DBGBVR11_EL1DBGBCR11_EL1DBGBVR12_EL1DBGBCR12_EL1DBGBVR13_EL1DBGBCR13_EL1DBGBVR14_EL1DBGBCR14_EL1DBGBVR15_EL1DBGBCR15_EL1syscalltlsfpsrfpcr @ @ aarch64_retval.ccount >= 1 && count <= 4count > 0size == 2 || size == 4 || size == 8 || size == 16tag == DW_TAG_structure_type || tag == DW_TAG_class_type || tag == DW_TAG_union_type || tag == DW_TAG_array_type33k2p303k2k2k2k2PQ@ABC@ABC@ABC@ABCpass_hfaphfa_typeaarch64_return_value_location HIJKLMNOsparc_reloc_valid_use#.<KZjz ,=JXhx.>N_is}-@Ti~!4G\q2K^jyR_SPARC_NONER_SPARC_8R_SPARC_16R_SPARC_32R_SPARC_DISP8R_SPARC_DISP16R_SPARC_DISP32R_SPARC_WDISP30R_SPARC_WDISP22R_SPARC_HI22R_SPARC_22R_SPARC_13R_SPARC_LO10R_SPARC_GOT10R_SPARC_GOT13R_SPARC_GOT22R_SPARC_PC10R_SPARC_PC22R_SPARC_WPLT30R_SPARC_COPYR_SPARC_GLOB_DATR_SPARC_JMP_SLOTR_SPARC_RELATIVER_SPARC_UA32R_SPARC_PLT32R_SPARC_HIPLT22R_SPARC_LOPLT10R_SPARC_PCPLT32R_SPARC_PCPLT22R_SPARC_PCPLT10R_SPARC_10R_SPARC_11R_SPARC_64R_SPARC_OLO10R_SPARC_HH22R_SPARC_HM10R_SPARC_LM22R_SPARC_PC_HH22R_SPARC_PC_HM10R_SPARC_PC_LM22R_SPARC_WDISP16R_SPARC_WDISP19R_SPARC_GLOB_JMPR_SPARC_7R_SPARC_5R_SPARC_6R_SPARC_DISP64R_SPARC_PLT64R_SPARC_HIX22R_SPARC_LOX10R_SPARC_H44R_SPARC_M44R_SPARC_L44R_SPARC_REGISTERR_SPARC_UA64R_SPARC_UA16R_SPARC_TLS_GD_HI22R_SPARC_TLS_GD_LO10R_SPARC_TLS_GD_ADDR_SPARC_TLS_GD_CALLR_SPARC_TLS_LDM_HI22R_SPARC_TLS_LDM_LO10R_SPARC_TLS_LDM_ADDR_SPARC_TLS_LDM_CALLR_SPARC_TLS_LDO_HIX22R_SPARC_TLS_LDO_LOX10R_SPARC_TLS_LDO_ADDR_SPARC_TLS_IE_HI22R_SPARC_TLS_IE_LO10R_SPARC_TLS_IE_LDR_SPARC_TLS_IE_LDXR_SPARC_TLS_IE_ADDR_SPARC_TLS_LE_HIX22R_SPARC_TLS_LE_LOX10R_SPARC_TLS_DTPMOD32R_SPARC_TLS_DTPMOD64R_SPARC_TLS_DTPOFF32R_SPARC_TLS_DTPOFF64R_SPARC_TLS_TPOFF32R_SPARC_TLS_TPOFF64R_SPARC_GOTDATA_HIX22R_SPARC_GOTDATA_LOX10R_SPARC_GOTDATA_OP_HIX22R_SPARC_GOTDATA_OP_LOX10R_SPARC_GOTDATA_OPR_SPARC_H34R_SPARC_SIZE32R_SPARC_SIZE64R_SPARC_WDISP10R_SPARC_JMP_IRELR_SPARC_IRELATIVER_SPARC_GNU_VTINHERITR_SPARC_GNU_VTENTRYR_SPARC_REV32SPARC_REGISTER    goliypsrwimtbrpcnpcfsrcsrpcnpcstatefsrfprsy)'')())))))))))(())')))')))))))()())()))))))))))))))))))))))))))))(x !"#XY F  A D @ B  @ S@T@@ R@P@U@bflushstbarswapmuldivv9ultra3v9vGNU_Sparc_HWCAPSGNU_Sparc_HWCAPS2gnu,fjathplusvis3badpsparc5mwaitxmpmulxmontnsecresv8resv9resv10resv11fjathhpcfjdesfjaesresv15resv16resv17resv18resv19resv20resv21resv22resv23resv24resv25resv26resv27resv28resv29resv30resv31mul32div32fsmuldpopcvisvis2asi_blk_initfmafvis3randomtransfjfmauimaasi_cache_sparingkasumicamelliamd5sha1sha256sha512pausecbcondcrc32c      !"#$%&'()*+,-./0123456789:;<=4?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefppc_reloc_valid_use &3CScp$/>M\lz ,6ESdu$9K`u0BTi~"5GXl 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h ! !!!!!!!!!! !!h !!!h !!!!!!! ! !!! !!!!!!!!!!!!!!!!!!!!!!!!!!!!! sf!STUVvectorprivilegedniporig_gpr3 r@t@s@d d C d  @ A  B m l e @ d w v bppcletruele3456789power6xdfppa6tarch_2_05ic_snoopsmtbookecellbepower5+power5power4notbefpdoubleefpsinglespeucache4xxmacmmufpualtivecppc601ppc64ppc32GNU_Power_ABI_FPGNU_Power_ABI_VectorGNU_Power_ABI_Struct_ReturnAnyr3/r4MemoryGenericAltiVecSPEHard or soft floatHard floatSoft floatSingle-precision hard floatA .opdppc64_reloc_valid_use,;M_q(9FWhy /BQ`v):FWk-AUlx/@Tk #:Qi $=Qh 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r@t@s@d d C d  @ A @ B@m@ l@(e@0@@8d@Hw@Pv@s390_reloc_valid_use &/:FR^ix%1=JYhw!0BTfv$-9HR_390_NONER_390_8R_390_12R_390_16R_390_32R_390_PC32R_390_GOT12R_390_GOT32R_390_PLT32R_390_COPYR_390_GLOB_DATR_390_JMP_SLOTR_390_RELATIVER_390_GOTOFF32R_390_GOTPCR_390_GOT16R_390_PC16R_390_PC16DBLR_390_PLT16DBLR_390_PC32DBLR_390_PLT32DBLR_390_GOTPCDBLR_390_64R_390_PC64R_390_GOT64R_390_PLT64R_390_GOTENTR_390_GOTOFF16R_390_GOTOFF64R_390_GOTPLT12R_390_GOTPLT16R_390_GOTPLT32R_390_GOTPLT64R_390_GOTPLTENTR_390_PLTOFF16R_390_PLTOFF32R_390_PLTOFF64R_390_TLS_LOADR_390_TLS_GDCALLR_390_TLS_LDCALLR_390_TLS_GD32R_390_TLS_GD64R_390_TLS_GOTIE12R_390_TLS_GOTIE32R_390_TLS_GOTIE64R_390_TLS_LDM32R_390_TLS_LDM64R_390_TLS_IE32R_390_TLS_IE64R_390_TLS_IEENTR_390_TLS_LE32R_390_TLS_LE64R_390_TLS_LDO32R_390_TLS_LDO64R_390_TLS_DTPMODR_390_TLS_DTPOFFR_390_TLS_TPOFFR_390_20R_390_GOT20R_390_GOTPLT20R_390_TLS_GOTIE20 pppppppppp@@@@@@pppppppppp@@@@@@xxxx@r`RSorig_r2system_calllast_breakhigh_r0high_r1high_r2high_r3high_r4high_r5high_r6high_r7high_r8high_r9high_r10high_r11high_r12high_r13high_r14high_r15fpc @ @@@!@)@1@9@A@I@Q@Y@a@i@q@y@@ A  H0  @ @@@!@)@1@9@A@I@Q@Y@a@i@q@y@@@A@@0      s390_initreg.cebl->class == ELFCLASS32s390_normalize_pcm68k_reloc_valid_use &1<FR^iv.<L\k{R_68K_NONER_68K_32R_68K_16R_68K_8R_68K_PC32R_68K_PC16R_68K_PC8R_68K_GOT32R_68K_GOT16R_68K_GOT8R_68K_GOT32OR_68K_GOT16OR_68K_GOT8OR_68K_PLT32R_68K_PLT16R_68K_PLT8R_68K_PLT32OR_68K_PLT16OR_68K_PLT8OR_68K_COPYR_68K_GLOB_DATR_68K_JMP_SLOTR_68K_RELATIVER_68K_TLS_GD32R_68K_TLS_GD16R_68K_TLS_GD8R_68K_TLS_LDM32R_68K_TLS_LDM16R_68K_TLS_LDM8R_68K_TLS_LDO32R_68K_TLS_LDO16R_68K_TLS_LDO8R_68K_TLS_IE32R_68K_TLS_IE16R_68K_TLS_IE8R_68K_TLS_LE32R_68K_TLS_LE16R_68K_TLS_LE8R_68K_TLS_DTPMOD32R_68K_TLS_DTPREL32R_68K_TLS_TPREL32 t"t"t"t"t"t"t"t""""""""""H%u$u$H%$H%H%H%H%H%H%H%H%H%H%$$H%H%u$H%H%H%u$H%H%H%H%H%H%H%$H%$H%H%$H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%H%$X`XPQ ` 8 < H     bpf_reloc_valid_use R_BPF_NONER_BPF_64_64R_BPF_64_32r%driscv_reloc_valid_use$5BTi~ /CVk#1>LZh~"/<IWevR_RISCV_NONER_RISCV_32R_RISCV_64R_RISCV_RELATIVER_RISCV_COPYR_RISCV_JUMP_SLOTR_RISCV_TLS_DTPMOD32R_RISCV_TLS_DTPMOD64R_RISCV_TLS_DTPREL32R_RISCV_TLS_DTPREL64R_RISCV_TLS_TPREL32R_RISCV_TLS_TPREL64R_RISCV_BRANCHR_RISCV_JALR_RISCV_CALLR_RISCV_CALL_PLTR_RISCV_GOT_HI20R_RISCV_TLS_GOT_HI20R_RISCV_TLS_GD_HI20R_RISCV_PCREL_HI20R_RISCV_PCREL_LO12_IR_RISCV_PCREL_LO12_SR_RISCV_HI20R_RISCV_LO12_IR_RISCV_LO12_SR_RISCV_TPREL_HI20R_RISCV_TPREL_LO12_IR_RISCV_TPREL_LO12_SR_RISCV_TPREL_ADDR_RISCV_ADD8R_RISCV_ADD16R_RISCV_ADD32R_RISCV_ADD64R_RISCV_SUB8R_RISCV_SUB16R_RISCV_SUB32R_RISCV_SUB64R_RISCV_GNU_VTINHERITR_RISCV_GNU_VTENTRYR_RISCV_ALIGNR_RISCV_RVC_BRANCHR_RISCV_RVC_JUMPR_RISCV_RVC_LUIR_RISCV_GPREL_IR_RISCV_GPREL_SR_RISCV_TPREL_IR_RISCV_TPREL_SR_RISCV_RELAXR_RISCV_SUB6R_RISCV_SET6R_RISCV_SET8R_RISCV_SET16R_RISCV_SET32R_RISCV_32_PCRELR_RISCV_IRELATIVER_RISCV_PLT32R_RISCV_SET_ULEB128R_RISCV_SUB_ULEB128"""""""""""""""""""""""""""""""""""""""""""""""""""""""""__global_pointer$RISCV_ATTRIBUTESRISCV_VARIANT_CC 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   ''''''''''$'$'$'$'d''$'$'$'$'$'$'$'$'$'$'$'$'$'$'$'''''''& $loongarch_reloc_valid_use$5BTi~6Kb} *:Nh6KXft #4EXk~ 1DWk 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!6R_ARC_NONER_ARC_8R_ARC_16R_ARC_24R_ARC_32R_ARC_N8R_ARC_N16R_ARC_N24R_ARC_N32R_ARC_SDAR_ARC_SECTOFFR_ARC_S21H_PCRELR_ARC_S21W_PCRELR_ARC_S25H_PCRELR_ARC_S25W_PCRELR_ARC_SDA32R_ARC_SDA_LDSTR_ARC_SDA_LDST1R_ARC_SDA_LDST2R_ARC_SDA16_LDR_ARC_SDA16_LD1R_ARC_SDA16_LD2R_ARC_S13_PCRELR_ARC_WR_ARC_32_MER_ARC_N32_MER_ARC_SECTOFF_MER_ARC_SDA32_MER_ARC_W_MER_ARC_SDA_12R_ARC_SDA16_ST2R_ARC_32_PCRELR_ARC_PC32R_ARC_GOTPC32R_ARC_PLT32R_ARC_COPYR_ARC_GLOB_DATR_ARC_JMP_SLOTR_ARC_RELATIVER_ARC_GOTOFFR_ARC_GOTPCR_ARC_GOT32R_ARC_S21W_PCREL_PLTR_ARC_S25H_PCREL_PLTR_ARC_JLI_SECTOFFR_ARC_TLS_DTPMODR_ARC_TLS_DTPOFFR_ARC_TLS_TPOFFR_ARC_TLS_GD_GOTR_ARC_TLS_GD_LDR_ARC_TLS_GD_CALLR_ARC_TLS_IE_GOTR_ARC_TLS_DTPOFF_S9R_ARC_TLS_LE_S9R_ARC_TLS_LE_32R_ARC_S25W_PCREL_PLTR_ARC_S21H_PCREL_PLTR_ARC_NPS_CMEM16ARC_ATTRIBUTES CSKY_ARCH_NAMECSKY_CPU_NAMECSKY_ISA_FLAGSCSKY_ISA_EXT_FLAGS./i386_data.hd->opoff1 % 8 + 4 <= 8%%es:(%%%sdi)$0x%x(*d->prefixes & prefix) == 0(%%%s%s)bxd->opoff1 / 8 == 2d->opoff1 % 8 == 2%%%s%xd->opoff1 % 8 == 0d->opoff1 / 8 == 5d->opoff1 % 8 + 3 <= 8acdb%%xmm%x%%mm%xd->opoff1 / 8 == 1d->opoff1 % 8 == 5%%st(%x)%s0x%xecsd-(%%b%c,%%%ci)(%%%s)%s0x%x(%%%n%s)! nodispxpd->opoff2 % 8 == 5%%%scltdcwtlINVALID not handledjecxzjcxzcwtdcbtwi386_disasm.cdata <= endlen > 0unknown prefixunknown suffix %d # <%s># %#lxr >= 0string_end_idx != ~0uld->opoff1 % 8 == 2 || d->opoff1 % 8 == 5d->opoff1 / 8 == d->opoff2 / 8curr + clen + 2 * (len - clen) <= match_endM   EM      ON AS]V:VV~USVVFCT_disp8FCT_mod$16r_mFCT_mod$8r_mFCT_selFCT_sreg2FCT_MOD$R_MFCT_Mod$R_mgeneric_absFCT_crdbFCT_ds_xxFCT_fregFCT_mod$r_m$wFCT_moda$r_mFCT_reg$wFCT_reg64FCT_sreg3FCT_mmxreggeneral_mod$r_mFCT_mod$r_mFCT_regFCT_xmmregonobaeenebeasnspnplgelegcmpeqcmpltcmplecmpunordcmpneqcmpnltcmpnlecmpordi386_disasm7" " ?88884f4$8 8  "4fT#T4fU#Ucb####8 ##88##80##8(88""""4"5@<88888:444f##8"444f'/8H80"w""""""""""""""""""""""""""""888 8(888 8(8088888 8("8 80"33"88"""80808088888888888(""8888888(8888 8088888(#i8@l"3#88p88 8(####8#8#8#80###88# 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E adcaddaddpdaddpsaddsdaddssaddsubpdaddsubpsandandnpdandnpsandpdandpsblendpdblendpsblendvpdblendvpsbsfbsrbswapbtbtcbtrbtscallclccldclflushclicltscmccmovcmpcmpeqpscmpeqsscmplepscmplesscmpltpscmpltsscmpneqpscmpneqsscmpnlepscmpnlesscmpnltpscmpnltsscmpordpscmpordsscmpscmpunordpscmpunordsscmpxchgcomisdcomisscpuidcvtdq2pdcvtdq2pscvtpd2dqcvtpd2picvtpd2pscvtpi2pdcvtpi2pscvtps2dqcvtps2pdcvtps2picvtsd2sicvtsd2sscvtsi2sdcvtsi2sscvtss2sdcvtss2sicvttpd2dqcvttpd2picvttps2dqcvttps2picvttsd2sicvttss2sidecdivdivpddivpsdivsddivssdppddppsemmsenterf2xm1fabsfaddfaddpfbldfbstpfchsfclexfcmovbfcmovbefcmovefcmovnbfcmovnbefcmovnefcmovnufcmovufcomfcomifcomipfcompfcomppfcosfdecstpfdivfdivpfdivrfdivrpffreefiaddficomficompfidivfidivlfidivrfidivrlfildfildlfildllfimulfincstpfinitfistfistpfistpllfisttpfisttpllfisubfisubrfldfld1fldcwfldenvfldl2efldl2tfldlg2fldln2fldpifldtfldzfmulfmulpfnclexfninitfnopfnsavefnstcwfnstenvfnstswfpatanfpremfprem1fptanfrndintfrstorfscalefsinfsincosfsqrtfstfstpfstptfsubfsubpfsubrfsubrpftstfucomfucomifucomipfucompfwaitfxamfxchfxrstorfxsavefxtractfyl2xfyl2xp1getsechaddpdhaddpshlthsubpdhsubpsidivimulinincinsinsertpsintint3invdinvlpgiretjjmplahflarlcalllddquldmxcsrlealeavelfencelfslgdtlgslidtljmplldtlmswlocklodslooploopeloopnelretlsllssltrmaskmovdqumaskmovqmaxpdmaxpsmaxsdmaxssmfenceminpdminpsminsdminssmonitormovmovapdmovapsmovdmovddupmovdq2qmovdqamovdqumovhlpdmovhlpsmovhpdmovhpsmovlhpdmovlhpsmovlpdmovlpsmovmskpdmovmskpsmovntdqmovntdqamovntimovntpdmovntpsmovntqmovqmovq2dqmovsmovsblmovsdmovshdupmovsldupmovslqmovssmovswlmovupdmovupsmovzblmovzwlmpsadbwmulmulpdmulpsmulsdmulssmwaitnegnopnotororpdorpsoutoutspabsbpabsdpabswpackssdwpacksswbpackusdwpackuswbpaddbpadddpaddqpaddsbpaddswpaddusbpadduswpaddwpalignrpandpandnpausepavgbpavgwpblendvbpblendwpcmpeqbpcmpeqdpcmpeqqpcmpeqwpcmpestripcmpestrmpcmpgtbpcmpgtdpcmpgtqpcmpgtwpcmpistripcmpistrmpextrwphadddphaddswphaddwphminposuwphsubdphsubswphsubwpinsrbpinsrdpinsrwpmaddubswpmaddwdpmaxsbpmaxsdpmaxswpmaxubpmaxudpmaxuwpminsbpminsdpminswpminubpminudpminuwpmovmskbpmovsxbdpmovsxbqpmovsxbwpmovsxdqpmovsxwdpmovsxwqpmovzxbdpmovzxbqpmovzxbwpmovzxdqpmovzxwdpmovzxwqpmuldqpmulhrswpmulhuwpmulhwpmulldpmullwpmuludqpoppopcntpopfporprefetchprefetchntaprefetcht0prefetcht1prefetcht2prefetchwpsadbwpshufbpshufdpshufhwpshuflwpshufwpsignbpsigndpsignwpslldpslldqpsllqpsllwpsradpsrawpsrldpsrldqpsrlqpsrlwpsubbpsubdpsubqpsubsbpsubswpsubusbpsubuswpsubwptestpunpckhbwpunpckhdqpunpckhqdqpunpckhwdpunpcklbwpunpckldqpunpcklqdqpunpcklwdpushpushfpushqpxorrclrcppsrcpssrcrrdmsrrdpmcrdtscretrolrorroundpdroundpsroundsdroundssrsmrsqrtpsrsqrtsssahfsarsbbscassetsfencesgdtshlshldshrshrdshufpdshufpssidtsldtsmswsqrtpdsqrtpssqrtsdsqrtssstcstdstistmxcsrstosstrsubsubpdsubpssubsdsubssswapgssyscallsysentersysexitsysrettestucomisducomissud2aunpckhpdunpckhpsunpcklpdunpcklpsverrverwvmcallvmclearvmlaunchvmptrldvmptrstvmreadvmresumevmwritevmxoffvmxonwbinvdwrmsrxaddxchgxlatxorxorpdxorpsr%1$d = %2$#lxr%1$d = map_fd(%2$#lx)call %1$dr0 = *(u8 *)skb[%1$d]r0 = *(u16 *)skb[%1$d]r0 = *(u32 *)skb[%1$d]r%1$d = le%2$d(r%1$d)r%1$d = be%2$d(r%1$d)r%1$d = (u32)r%1$d + %2$dr%1$d = (u32)r%1$d - %2$dr%1$d = (u32)r%1$d * %2$dr%1$d = (u32)r%1$d / %2$dr%1$d = (u32)r%1$d | %2$#xr%1$d = (u32)r%1$d & %2$#xr%1$d = (u32)r%1$d << %2$dr%1$d = (u32)r%1$d >> %2$dr%1$d = (u32)r%1$d %% %2$dr%1$d = (u32)r%1$d ^ %2$#xr%1$d = %2$#xr%1$d += %2$dr%1$d -= %2$dr%1$d *= %2$dr%1$d /= %2$dr%1$d |= %2$dr%1$d &= %2$dr%1$d <<= %2$dr%1$d >>= %2$dr%1$d %%= %2$dr%1$d ^= %2$dr%1$d = %2$dr%1$d = (s64)r%1$d >> %2$dr0 = *(u8 *)skb[r%1$d+%2$d]r0 = *(u16 *)skb[r%1$d+%2$d]r0 = *(u32 *)skb[r%1$d+%2$d]r%1$d = (u32)r%2$dr%1$d += r%2$dr%1$d -= r%2$dr%1$d *= r%2$dr%1$d /= r%2$dr%1$d |= r%2$dr%1$d &= r%2$dr%1$d <<= r%2$dr%1$d >>= r%2$dr%1$d %%= r%2$dr%1$d ^= r%2$dr%1$d = r%2$dr%1$d = (s64)r%1$d >> r%2$dr%1$d = (u32)-r%1$dr%1$d = -r%1$dif r%1$d == %2$d goto %3$#xif r%1$d > %2$d goto %3$#xif r%1$d >= %2$d goto %3$#xif r%1$d & %2$d goto %3$#xif r%1$d != %2$d goto %3$#xif r%1$d < %2$d goto %3$#xif r%1$d <= %2$d goto %3$#xif r%1$d == r%2$d goto %3$#xif r%1$d > r%2$d goto %3$#xif r%1$d >= r%2$d goto %3$#xif r%1$d & r%2$d goto %3$#xif r%1$d != r%2$d goto %3$#xif r%1$d < r%2$d goto %3$#xif r%1$d <= r%2$d goto %3$#x*(u8 *)(r%1$d%3$+d) = %2$d*(u16 *)(r%1$d%3$+d) = %2$d*(u32 *)(r%1$d%3$+d) = %2$d*(u64 *)(r%1$d%3$+d) = %2$dr%1$d = *(u8 *)(r%2$d%3$+d)r%1$d = *(u16 *)(r%2$d%3$+d)r%1$d = *(u32 *)(r%2$d%3$+d)r%1$d = *(u64 *)(r%2$d%3$+d)*(u8 *)(r%1$d%3$+d) = r%2$d*(u16 *)(r%1$d%3$+d) = r%2$d*(u32 *)(r%1$d%3$+d) = r%2$d*(u64 *)(r%1$d%3$+d) = r%2$dgoto %1$#xinvalid class %sr%1$d = ld_pseudo(%3$d, %2$#lx)r%1$d = (u32)((s32)r%1$d >> %2$d)r%1$d = (u32)r%1$d + (u32)r%2$dr%1$d = (u32)r%1$d - (u32)r%2$dr%1$d = (u32)r%1$d * (u32)r%2$dr%1$d = (u32)r%1$d / (u32)r%2$dr%1$d = (u32)r%1$d | (u32)r%2$dr%1$d = (u32)r%1$d & (u32)r%2$dr%1$d = (u32)r%1$d << (u32)r%2$dr%1$d = (u32)r%1$d >> (u32)r%2$dr%1$d = (u32)r%1$d %% (u32)r%2$dr%1$d = (u32)r%1$d ^ (u32)r%2$dr%1$d = (u32)((s32)r%1$d >> r%2$d)if (s64)r%1$d > %2$d goto %3$#xif (s64)r%1$d >= %2$d goto %3$#xif (s64)r%1$d < %2$d goto %3$#xif (s64)r%1$d <= %2$d goto %3$#xif (s64)r%1$d > (s64)r%2$d goto %3$#xif (s64)r%1$d >= (s64)r%2$d goto %3$#xif (s64)r%1$d < (s64)r%2$d goto %3$#xif (s64)r%1$d <= (s64)r%2$d goto %3$#xlock *(u32 *)(r%1$d%3$+d) += r%2$dlock *(u64 *)(r%1$d%3$+d) += r%2$dS;G #/am&,dS~nzp|2>JVb+y !-9EQ]iu'3?KWco{ldldxststxalujmp6alu64c.addisext.waddiwc.liflwsraisrliandic.mvc.addbeqzbnezfswsext.auipcluinegnegwzerofmin.fmax.csrrcsrccsrwfencesgtzjrmretcsrsbleusltzsnezblezfence.tsojaljalrbgtzfence.icsrsisreturetebreakecallwfic.nopunimpfsdfldc.sllinotseqzriscv_disasm.c%lu%lu(%s)%ld(%s)%u(%s)%ld0x%04xcp[-1] != ' '%u0x%08x wd csrrwcsrrscsrrccsrrwicsrrsicsrrciustatusfflagsframfcsruieutvecuscratchuepcucauseutvaluipsedelegsidelegscounterenvsstatusvsievstvecvsscratchvsepcvscausevstvalvsipvsatphstatushedeleghideleghtimedeltahcounterenhtimedeltahhgatphpmcounter3hpmcounter4hpmcounter5hpmcounter6hpmcounter7hpmcounter8hpmcounter9hpmcounter10hpmcounter11hpmcounter12hpmcounter13hpmcounter14hpmcounter15hpmcounter16hpmcounter17hpmcounter18hpmcounter19hpmcounter20hpmcounter21hpmcounter22hpmcounter23hpmcounter24hpmcounter25hpmcounter26hpmcounter27hpmcounter28hpmcounter29hpmcounter30hpmcounter31cyclehtimehinstrethhpmcounter3hhpmcounter4hhpmcounter5hhpmcounter6hhpmcounter7hhpmcounter8hhpmcounter9hhpmcounter10hhpmcounter11hhpmcounter12hhpmcounter13hhpmcounter14hhpmcounter15hhpmcounter16hhpmcounter17hhpmcounter18hhpmcounter19hhpmcounter20hhpmcounter21hhpmcounter22hhpmcounter23hhpmcounter24hhpmcounter25hhpmcounter26hhpmcounter27hhpmcounter28hhpmcounter29hhpmcounter30hhpmcounter31hfsflagsifsrmifsflagsfsrmfssrrdcyclerdtimerdinstretfrflagsfrrmfrsrbeqbnebltbgebltubgeufsgnj.fsgnjn.fsgnjx.fmv.fneg.fabs.flefltfeqfaddfsubfmulfdivrnertzrdnruprmmdynfmadd.fmsub.fnmsub.fnmadd.addwsllwsrlwsubwsrawmulwdivwdivuwremwremuwsllsltsltusrlsramulhmulhsumulhudivuremremu.rl.aq.aqrlamoaddamoswapamoxoramooramoandamominamomaxamominuamomaxufsqsbsltisltiuxoriunknownirirwioiowioriorwflqlblbulwuft0ft1ft2ft3ft4ft5ft6ft7fs0fs1fa0fa1fa2fa3fa4fa5fa6fa7fs2fs3fs4fs5fs6fs7fs8fs9fs10fs11ft8ft9ft10ft11gp  X h X h ` +cAa(IzOfkq_k.x.x.x.x.x.x.x.x.x .xT wdqsdqriscv_disasmmemory exhaustedELFUTILS_COLORS[%.*smcolorWHEN%s: invalid argument '%s' for '--color' valid arguments are: - 'always', 'yes', 'force' - 'never', 'no', 'none' - 'auto', 'tty', 'if-tty' colorize the output. WHEN defaults to 'always' or can be 'auto' or 'never'alwaysyesforcenevernononeautottyif-tty%s (%s) %s http://elfutils.org/2023Copyright (C) %s The elfutils developers <%s>. This is free software; see the source for copying conditions. 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